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Senior Verification Engineer - Core Testbench & DV Methodology Lead

Hireroo
2 days ago
Full-time
On-site
Barcelona, Spain
Engineering and Data

Job Description

Our partner is looking for a Senior or Principal Verification Engineer to own the core level verification environment, methodology, tooling and CI infrastructure for complex processor designs.

The role focuses on evolving the top level UVM testbench, integrating unit level VIP, driving functional and code coverage closure, improving verification flows and identifying gaps between processor units. You will also act as a senior technical reference for verification methodology, testbench architecture and cross unit quality.

Location: Barcelona, Spain, Hybrid
Level: Senior / Principal

Responsibilities

  • Own and evolve the core level UVM testbench

  • Integrate unit level VIP into top level verification

  • Drive functional and code coverage closure

  • Identify and close cross unit verification gaps

  • Review assume and guarantee relationships between blocks

  • Own regression, compile and coverage flows

  • Maintain and improve verification CI infrastructure

  • Improve verification methodology, tooling and automation

  • Review block and core level testbench architecture

  • Mentor verification engineers and provide technical guidance

  • Work with EDA vendors and internal engineering teams

  • Support improvements to coverage driven and assertion based verification

Requirements

  • 10+ years of design verification experience

  • Processor core or complex microarchitecture verification

  • RISC V experience highly valued

  • Expert SystemVerilog and UVM

  • Reusable and configurable multi agent testbench development

  • Strong functional coverage and verification planning

  • Coverage closure at core or top level

  • Deep Questa experience

  • Visualizer, Verdi or similar debug tools

  • Strong Python, plus Bash or Tcl

  • Verification CI and regression ownership

  • SVA and assertion based verification

  • Cross block verification and assume/guarantee reasoning

  • B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering or related field

Optional / Desired

  • RISC V core verification

  • Formal verification

  • Veloce or ZeBu

  • AXI or CHI

  • Processor verification methodology ownership

  • Experience mentoring verification engineers

  • EDA flow and tool migration experience

What’s in it for you?

  • Flexible working hours

  • Hybrid model, 4 days office, 1 day from home

  • 1 week per year working from anywhere

  • 25 days annual leave plus December 24 and 31

  • Monthly food allowance

  • Private medical insurance

  • Relocation bonus

  • Housing search support

  • Visa support if required

  • Family relocation support

  • Virtual shares

  • Language classes

  • Tax incentive, subject to eligibility